Register file design verilog

Two bit output register read data signals: rdata1 and rdata2. One bit input register write data signals: wdata. One 1-bit input register write enable signal for the single write port: wen.

One 1-bit input reset signal: rst. One 1-bit input clock signal: clk. As before, we'll use a multi-level modular design: 1. Register File Create a register file module with the interface specified above. Demos Similar to the demo for lab 1, the TAs will run an additional test input file to test additional cases.

What to Turn In Turn in: Verilog code. As before, your Verilog code should be well-formatted, easy to understand, and include comments where appropriate for example, use comments to describe all the inputs and outputs to your Verilog modules. Some part of the project grade will be dependent on the style and readability of your Verilog, including formatting, comments, good signal names, and proper use of hierarchy.

Hand-drawn schematic. Turn in a schematic for the register file. You need not turn in schematics for the multiplexor or decoder. What is the delay in nanoseconds and resource usage for your register file. How do these compare to the delay and resource usage of your ALU? What problems, if any, did you encounter while doing this lab? How many hours did it take you to complete this assignment?

On a scale of 1 least to 5 most , how difficult was this assignment? If there is a cyclic path of logic from a register's output to its input, then the circuit is called a state machine or sequential logic. If there are logic paths from a register to another without a cycle, then it is called a pipeline. RTL is used in the logic design phase of the integrated circuit design cycle.

An RTL description is converted into a gate-level description of the circuit by a logic synthesis tool. The synthesis results are then used by placement and routing tools to create a physical layout. Logic simulation tools may use a design's RTL description to verify its correctness.

The most accurate power analysis tools are available for the circuit level, but even with a switch rather than device-level modelling, tools at the circuit level have disadvantages. They are either too slow or require too much memory. The majorities of these are simulators like SPICE and used by the designers for many years as performance analysis tools. Due to these disadvantages, gate-level power estimation tools have begun to gain some acceptance where faster, probabilistic techniques have begun to gain a foothold.

But it also has its trade-off as speedup is achieved on the cost of accuracy, especially in the presence of correlated signals.

Over the years, it has been realized that the low power design cannot come from the circuit- and gate-level optimizations. In contrast, system, architecture, and algorithm optimizations tend to have the largest impact on power consumption. Therefore, there has been a shift in the tool developers' incline towards high-level analysis and optimization tools for power. It is a technique based on the concept of gate equivalents. The complexity of chip architecture can be described approximately in terms of gate equivalents, where the equivalent gate count specifies the average number of reference gates that are required to implement the particular function.

The total power required for the particular function is estimated by multiplying the approximated gate equivalents with the average power consumed per gate. The reference gate can be any gate, e. This technique is distributed in the following types, such as:.

Class Independent Power Modeling: It is a technique which tries to estimate chip area, speed, and power dissipation based on information about the complexity of the design in terms of gate equivalents. The functionality is divided among different blocks, but no distinction is made about the functionality of the blocks. It is class independent. This technique completes the following steps:. Step 1: Identify the functional blocks such as counters, decoders, multipliers, memories , etc.

Step 2: Assign a complexity in terms of Gate Equivalents. The number of GE's for each unit type are either taken directly as an input from the user or fed from a library. Class Depedent Power Modeling: This approach is slightly better than the previous approach as it takes into account customized estimation techniques to the different types of functional blocks. Therefore it is trying to increase the modelling accuracy, which wasn't in the case of previous techniques such as logic, memory, interconnects , and clocks.

The power estimation is done in a very similar manner to the independent case. The basic switching energy is based on a three-input AND gate and is calculated from technology parameters, e. This technique further customizes the power estimation of various functional blocks by having a separate power model for logic, memory, and interconnects.

These suggest a Power Factor Approximation PFA method for individually characterizing an entire library of functional blocks such as multipliers, adders, etc.

RD RD ,. WR WR ,. EN EN ,. Timing diagram of Register File. Email This BlogThis! Subscribe to: Posts Atom. Block Diagram of Register File Read operation. Block Diagram of Register File Write operation. Verilog module of the Register File. Figure 4.